The present invention relates to a microprocessor, and more particularly, technology to be utilized in a microprocessor incorporating a program wait circuit for asynchronous data aquisition. The invention is particularly relevant to interfacing a central processor with a direct memory interface device.
In microprocessors of the 68000 series variety which incorporate a program wait circuit, data from peripheral devices, such as memory, is received in the following manner. At a state "0", specified by a clock (machine cycle) signal, an address bus is taken to a high impedance state. A read/write signal ("R/W") is made high to indicate the presence of the read cycle.
At a state "2", an address strobe signal (typically "AS") is made active, which is defined at a low level. This indicates that an effective address signal exists on the address bus. Peripheral devices, such as memory, together with the address bus, receive the address strobe signal, and individually determine whether they are selected. When a device is selected, it becomes active, and transmits an appropriate data signal onto the data bus.
A wait time of a program wait circuit is set, taking into account access time necessary for the particular selected device, such as the time necessary to access a selected memory. That is, one or more wait cycles are set for a selected device having a relatively low access speed.
At completion of the wait cycles, it is presumed that effective data exists on the data bus, and the data is read therefrom.
A microprocessor incorporating a program wait circuit as above-described is disclosed in, for example, "Hitachi Microcomputer Data Book, 8 bits/16 bits Microprocessor", pages 462-463, published in Sept. 1985 by Hitachi, Ltd.
When a bus control or bus master system is contained solely in a microprocessor, the selected device can be accessed without severe problems. However, if the system incorporates a device such as a slave microprocessor or a direct memory access device, a control circuit will be necessary to command the above-mentioned wait cycle.